As we know that our chips now a days are loaded with large number of features hence the size of the designs are growing at a rapid pace. Modern SoC/ASICs are getting bigger & bigger in terms of gate counts as well as supported features. In such scenarios, the major challenges are to achieve stiff time-to-market and performing satisfactory Functional Verification of such large ASIC/SoC.
Primarily following technologies are being used to achieve Functional Verification Closure:
- RTL Simulation
- Formal or Static Verification
- FPGA Prototyping
The technology which is getting popular in Functional Verification Flow to support these challenges is “Emulation“. So a obvious curiosity is to know “What is Emulation?” and “How it works?“. I’ll cover – “What is Emulation?” part in this post.
Lets know What actually Emulation is? Emulation is the use of a specialist computer (popularly called “Emulator“) which automatically maps the RTL representation of a Design to its internal programmable gate-array to perform the Functional Verification of the Hardware and Software of the Design.
Now lets see what are the motivations behind adopting Emulation as part of the Verification Flow?
- Increasing gate-count of the SoC designs. A typical SoC now a days contains approx. 50 Million gates. Simulators are practically not that efficient in terms of performance to handle such big designs.
- Time-to-market pressures means that strategies that enable more efficient hardware/software co-verification are becoming increasingly attractive. Emulation offers this despite a comparatively high upfront cost.
- Emulators offer shorter compile times as well as far greater debug and waveform visibility than FPGA Prototyping
- The system-level capabilities of today’s emulators enable their use earlier in design projects than before to assist in decisions made at higher levels of abstraction. This also helps justify their cost.
- Today’s emulators are architect-ed both for use in the cloud (they can thus be shared by geographically spread design teams) and scalability (several can be connected for use on the same project to further reduce run-times).
- Embedded Software validation.
Lets elaborate the point no. 1 above with some benchmark data –
Executing the real data of 1 second in a 100-million-gate circuit designed to run at 200 MHz would require the execution of 200 million cycles. Even on the fastest CPU with a generous cache size and a vast amount of RAM, an RTL Simulator would require more than three weeks at 100 cycles per second –– an optimistic assumption –– to run through the design. It clearly shows that RTL Simulation is not an efficient way for big designs to execute real time data for meaningful time. If small time-frame is ONLY tested, it might leave scope for many possible gaps and bugs being uncovered.
Comparing Different Verification Technologies:
In the shown diagrams below, the comparison between different Verification Technologies i.e. RTL Simulation, FPGA Prototyping & Modern Emulation is shown with respect to various parameters e.g.
- Design Capacity
- Setup & Compile Time
- Design Debug Capability
Diagram 1: Comparison of RTL simulation, FPGA prototyping, and Hardware Emulation is based on performance, setup/compile time, design capacity, and design debug. (Source: Dr. Lauro Rizzatti)
In the Diagram 2 below, supported features are shown for different options:
Diagram 2: Features supported for different Technologies (Source: Dr. Lauro Rizzatti)
The advanced Emulators provided by the market’s three main players – Cadence Design Systems (Palladium XP), Mentor Graphics (Veloce) and Synopsys (ZeBu) – are all capable of handling both system-level (e.g. C, C++, transaction-level models) and RTL designs.
This is an introductory information about Emulation Technology with comparison to other options like RTL Simulation & FPGA prototyping. I’ll add more post related to the Emulation and will try to add more information to this post as well. So please keep re-visiting the site for updated information. I believe this post will help you to provide basic info about Emulation. Thank you for your time.
See you again with more information! Till then..Bye..Take Care! 🙂